ASIC Digital Verification, Staff Engineer

Category Engineering Hire Type Employee Job ID 6932 Remote Eligible No Date Posted 26/10/2024

And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

The position offers an excellent opportunity to work with an expert team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs from creating test plans to performing functional and performance tests on the test-chips/products.

• Creating and updating test plans and test cases
• Writing modular constrained-random/coverage driven Verilog, SystemVerilog
• and UVM/VMM testbenches
• Writing SystemVerilog assertions
• Monitoring simulation regressions and debugging RTL and Gate level simulation failures
• Writing functional coverage and performing functional/code/assertion coverage analysis
• Tracking/Reporting issues in Jira and documenting in Confluence

Skills required:

• BS/MS in Electronics / Electrical Engineering or related fields with 5+ years of industry experience with digital verification methodology such as VMM/UVM
• Solid experience in writing testcases in Verilog and System Verilog
• Solid experience in debugging complex testbench and design related issues
• Solid understanding of digital circuit design
• Basic understanding of C/C++ and RISC processors
• Familiarity with scripting languages (Python or Perl)
• Self learner/independent, good organization and communication skills

Skills desired:

• Knowledge of high-speed digital & mixed-signal design
• System Verilog Assertions / formal verification
• Good organization and communication skills